Altera Transceiver PHY IP Core - Manual (Page 368)

Figure 12-8: x6 and xN Routing of Clocks
Transceiver Bank
Transceiver Bank
×N_top
Clock Line (1)
×6 Clock Lines (1)
×6 Clock Lines (1)
×N_bottom
Clock Line (1)
x6 Clock Lines
xN Clock Lines
Ch5
Local Clock
Divider
Ch4
Central Clock
Divider
Ch3
Local Clock
Divider
Ch2
Local Clock
Divider
Ch1
Central Clock
Divider
Ch0
Local Clock
Divider
Ch5
Local Clock
Divider
Ch4
Central Clock
Divider
Ch3
Local Clock
Divider
Ch2
Local Clock
Divider
Ch1
Central Clock
Divider
Ch0
Local Clock
Divider
Serial and Parallel Clocks
Note: (1) The the x6 and xN clock lines also carry both serial and parallel clocks.
12-70 ×6/×N Bonded Clocking
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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