Altera Transceiver PHY IP Core - Manual (Page 253)

Name Value Description
Data rate Device
dependent
Specifies the data rate in Mbps. Refer to
Stratix V Device Datasheet for the data rate
ranges of datapath.
Base data rate 1 × Data rate
2 × Data rate
4 × Data rate Select a base data rate that minimizes the
number of PLLs required to generate all the
clocks required for data transmission. By
selecting an appropriate base data rate, you
can change data rates by changing the
divider used by the clock generation block.
For higher frequency data rates 2 × and 4×
base data rates are not available.
Input clock frequency Variable Specifies the frequency of the PLL input
reference clock. The Input clock frequency
drop down menu is populated with all valid
frequencies derived as a function of the data
rate and base data rate. However, if you
select
fb_compensation
as the bonding
mode, then the input reference clock
frequency is limited to the (data rate) /
(PCS-PMA interface width).
The following table lists Standard and 10G datapath widths for the FPGA fabric-transceiver interface, the
PCS-PMA interface, and the resulting frequencies for the
tx_clkout
and
rx_clkout
parallel clocks. In
almost all cases, the parallel clock frequency is described by the following equation:
frequency
parallel clock
= data rate/FPGA fabrictransceiver interface width
Note: The FPGA fabric transceiver interface width is always 128 bits for the GT datapath.
Table 10-4: Datapath Width Support
FPGA Fabric -
Transceiver Interface
Width
PCS-PMA Interface Width
tx_clkout and rx_clkout frequency
Standard Datapath
10G Datapath
8 8 — data rate/8
10 10 — data rate/10
16 8 or 16 — data rate/16
20 10 or 20 — data rate/20
32 16 32 data rate/32
40 20 40 data rate/40
10-6 General Options Parameters
UG-01080
2015.01.19
Altera Corporation Low Latency PHY IP Core
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