Altera ALTDQ_DQS2 - Manual

ALTDQ_DQS2 IP Core User Guide
2014.12.17
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The Altera ALTDQ_DQS2 megafunction IP core controls the double data rate (DDR) I/O elements
(IOEs) for the data (DQ) and data strobe (DQS) signals in Arria ® V, Cyclone ® V, and Stratix ® V devices.
A DQ group is composed of one DQS, one optional complementary DQS, and up to 36 configurable DQ
I/Os.
Related Information
Introduction to Altera IP Cores
ALTDQ_DQS2 Features
The ALTDQ_DQS2 IP core has the following features:
• Access to dynamic on-chip termination (OCT) controls to switch between parallel termination during
reads and series termination during writes.
• High-performance support for DDR interface standards.
• 4- to 36-bit programmable DQ group widths.
• Half-rate registers to enable successful data transfers between the I/O registers and the core logic.
• Access to I/O delay chains to fine-tune delays on the data or strobe signals.
• Access to hard read FIFO.
• Access to latency shifter FIFO and data valid FIFO for efficient control of DQS gating and read
operations (Arria V and Cyclone V devices only).
ALTDQ_DQS2 Device Support
The ALTDQ_DQS2 IP core supports the following devices:
• Arria V devices
• Cyclone V devices
• Stratix V devices
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