Altera Transceiver PHY IP Core User Manual
Page 303
Name
Range
Description
Number of data channels
Device
Dependent
Specifies the total number of data channels in each
direction. From 1-32 channels are supported.
Bonding mode
Non-bonded or
x1
×6/×N
fb_compensa‐
tion
In Non-bonded or x1 mode, each channel is paired with a
PLL. If one PLL drives multiple channels, PLL merging is
required. During compilation, the Quartus II Fitter,
merges all the PLLs that meet PLL merging requirements.
Refer to
Merging TX PLLs In Multiple Transceiver PHY
on page 16-57 to observe PLL merging rules.
When you select ×6/×N Bonding Mode, the Quartus II
software uses a single TX PLL to generate the clock for up
to 6 channels in a single transceiver bank. If the channels
used cross a transceiver bank boundary, the Quartus II
software uses the ×N clock lines to route the same clock
source to the channels.
Bonded channels do not support dynamic reconfiguration
of the transceiver.
Select fb_compensation (feedback compensation) to use
the same clock source for multiple channels across
different transceiver banks to reduce clock skew. For more
information about bonding, refer to "Bonded Channel
Configurations Using the PLL Feedback Compensation
Path" in volume 2 of the Stratix V Device Handbook.
Enable simplified data
interface
On/Off
When you turn this option On, the Native PHY presents
only the relevant data bits. When you turn this option Off,
the Native PHY presents the full raw interface to the fabric.
If you plan to dynamically reconfigure the Native PHY,
you must turn this option Off and you need to understand
the mapping of data to the FPGA fabric. Refer to
for more information. When you turn this option
On , the Native PHY presents an interface that includes
only the data necessary for the single configuration
specified.
Related Information
UG-01080
2015.01.19
General Parameters for Stratix V Native PHY
12-5
Stratix V Transceiver Native PHY IP Core
Altera Corporation