Altera Transceiver PHY IP Core - Manual (Page 592)

Parameterizing the Transceiver PLL PHY
The IP Catalog provides the following Transceiver PLL IP Cores: Arria V Transceiver, Arria V GZ
Transceiver PLL, and Stratix V Transceiver PLL to be used with the Arria V, Arria V GZ and Stratix V
Native PHYs, respectively.
Complete the following steps to configure a Transceiver PLL IP Core:
1. Under Tools > IP Catalog, select the device familyof your choice.
2. Under Tools > IP Catalog > Interface Protocols > Transceiver PHY> Transceiver PLL
.
3. Specify the options required for the PLL.
4. Click Finish to generate your parameterize Transceiver PLL IP Core.
Transceiver PLL Parameters
Table 18-1: PLL Reconfigurations
Name Value Description
Enable PLL Reconfiguration On/Off You must enable this option if you plan to
reconfigure the PLLs in your design. This
option is also required to simulate PLL
reconfiguration.
Number of TX reference clocks 1-5
Specifies the number of reference clocks
inputs to the Transceiver PLL.
PLL feedback path Internal
External
Select the External feedback path for the
CPRI protocol to improve clock jitter by
using an external voltage controlled crystal
oscillator (VCXO). Select Internal for all
other protocols.
PLL Type
CMU
ATX
Specifies the PLL type. You must select the
CMU PLL for designs that also include a
fractional PLL. The ATX pll is available for
Stratix V and Arria V GZ devices.
PLL base data rate
1 × Lane rate
2 × Lane rate
4 × Lane rate
8 × Lane rate
Specifies Base data rate. This value should
match the value specified in the Native PHY.
UG-01080
2015.01.19
Parameterizing the Transceiver PLL PHY 18-3
Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices Altera Corporation
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