Altera Transceiver PHY IP Core User Manual
Page 655
Table 20-5: PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals
Stratix IV GX Device Signal Name
(21)
Stratix V GX Device Signal Name
Width
Reference Clocks and Resets
pll_inclk
pll_ref_clk
1
rx_cruclk
Not available
[<n> -1:0]
tx_coreclk
Not available
[<n> -1:0]
rx_coreclk
Not available
[<n> -1:0]
tx_clkout/coreclkout
pipe_pclk
1
pll_powerdown
These signals are now available as
control and status registers. Refer to
the "Avalon-MM PHY Management
Interface and PCI Express PHY
(PIPE) IP Core Registers".
1
cal_blk_powerdown
1
Not available
tx_ready
(reset control status)
1
Not available
rx_ready
(reset curl status)
1
PIPE interface Ports
tx_datain
pipe_txdata
[<n><d>-1:0]
tx_ctrlenable
pipe_txdatak
[(<d>/8)*<n>-1:0]
tx_detectrxloop
pipe_txdetectrx_loopback
[<n> -1:0]
t
x_forcedispcompliance
pipe_txcompliance
[<n> -1:0]
tx_forceelecidle
pipe_txelecidle
[<n> -1:0]
txswing
pipe_txswing
[<n> -1:0]
tx_pipedeemph[0]
pipe_txdeemph
[<n> -1:0]
tx_pipemargin[2:0]
pipe_txmargin
[3<n>-1:0]
rateswitch[0]
pipe_rate[1:0]
[<n>-1:0]
powerdn
pipe_powerdown
[2<n>-1:0]
rx_elecidleinfersel
pipe_eidleinfersel
[3<n>-1:0]
rx_dataout
pipe_rxdata
[<n>-*<d>-1:0]
rx_ctrldetect
pipe_rxdatak
[(<d>/8)*<n>-1:0]
pipedatavalid
pipe_rxvalid
[<n>-1:0]
pipe8b10binvpolarity
pipe_rxpolarity
[<n>-1:0]
pipeelecidle
pipe_rxelecidle
[<n>-1:0]
(21)
<n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
UG-01080
2013.12.20
Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V
Devices
20-9
Migrating from Stratix IV to Stratix V Devices Overview
Altera Corporation