Altera Transceiver PHY IP Core User Manual
Page 518
Transceiver Reconfiguration Controller IP Core
Overview
16
2015.01.19
UG-01080
The Altera Transceiver Reconfiguration Controller dynamically reconfigures analog settings in Arria V,
Arria V GZ, Cyclone V, and Stratix V devices. Dynamic reconfiguration allows you to compensate for
variations due to process, voltage, and temperature (PVT) in 28-nm devices.
Dynamic reconfiguration is required for Arria V, Arria V GZ, Cyclone V, and Stratix V devices that
include transceivers. The reconfiguration functionality available in Arria V and Cyclone V devices is a
subset of the functionality available for Stratix V devices.
Note: Some of the reconfiguration features not available for Arria V and Cyclone V devices in the current
release, may be available in subsequent releases. Arria V and Cyclone V devices do not include
ATX PLLs. Stratix V and Arria V GZ devices include ATX PLLs.
Table 16-1: Device Support for Dynamic Reconfiguration
Area
Feature
Stratix V
Arria V
Arria V GZ
Cyclone V
Calibration
Functions
Offset cancellation
Yes
Yes
Yes
Yes
Duty cycle distortion calibration —
Yes
—
Yes
ATX PLL calibration
Yes
—
Yes
—
Analog Features
On-chip signal quality
monitoring
Yes
—
Yes
—
Decision feedback equalization
(DFE)
Yes
—
Yes
—
Adaptive equalization
Yes
—
Yes
—
Loopback modes
Pre-CDR reverse serial loopback Yes
Yes
Yes
Yes
Post-CDR reverse serial loopback Yes
Yes
Yes
Yes
PLL reconfigura‐
tion
Reference clock switching (CDR,
ATX PLLs, and TX PLLs)
Yes
Yes
Yes
Yes
TX PLL connected to a
transceiver channel
reconfiguration
Yes
Yes
Yes
Yes
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