Altera Transceiver PHY IP Core User Manual
Page 542
Table 16-15: AEQ Registers
Reconfig Addr
Bits
R/W
Register Name
Description
7’h28
[9:0] RW
logical channel number
The logical channel number of the AEQ
hardware to be accessed. Must be specified
when performing dynamic updates. The
Transceiver Reconfiguration Controller
maps the logical address to the physical
address.
7’h2A
[9]
R
control and status
Error
.When asserted, indicates an error.
This bit is asserted when the channel
address is invalid.
[8]
R
Busy
. When asserted, indicates that a
reconfiguration operation is in progress.
[1]
W
Read
. Writing a 1 to this bit triggers a read
operation.
[0]
W
Write
. Writing a 1 to this bit triggers a
write operation.
7’h2B
[3:0] RW
aeq_offset
Specifies the address of the AEQ register to
for details.
7’h2C
[15:0] RW
data
Specifies the read or write data.
The following table describes the AEQ registers that you can access to change AEQ settings.
Note: All undefined register bits are reserved.
UG-01080
2015.01.19
Transceiver Reconfiguration Controller AEQ Registers
16-25
Transceiver Reconfiguration Controller IP Core Overview
Altera Corporation