Altera Transceiver PHY IP Core - Manual (Page 531)

Auxiliary Transmit (ATX) PLL Calibration
ATX calibration tunes the parameters of the ATX PLL for optimal performance. This function runs once
after power up. You can rerun this function by writing into the appropriate memory-mapped registers.
The RX buffer is unavailable while this function is running. You should run the ATX calibration after
reconfiguring the PLL. You may need to rerun ATX calibration if you reset an ATX PLL and it does not
lock after the specified lock time.
For more information about the Auxiliary Transmit (ATX) PLL Calibration refer to ATX PLL Calibration
Registers.
Refer to the Parameterizing the Transceiver Reconfiguration Controller IP Core in the MegaWizard Plug-In
Manager section for information about how to enabled these functions.
Note: If you are using a PHY IP with DFE enabled with a reconfiguration controller and/or if you are
using ATX PLLs in your design, then the reference clock to the PHY IP must be stable before the
reconfiguration controller is taken out of reset state.
Transceiver Reconfiguration Controller PMA Analog Control Registers
You can use the Transceiver Reconfiguration Controller to reconfigure the following analog controls:
• Differential output voltage (V
OD
)
• Pre-emphasis taps
• Receiver equalization control
• Receiver equalization DC gain
• Reverse serial loopback
Note: All undefined register bits are reserved.
Table 16-9: PMA Analog Registers
Reconfig Addr Bits R/W Register Name Description
7’h08 [9:0] RW
logical channel number
The logical channel number. Must be
specified when performing dynamic
updates. The Transceiver Reconfiguration
Controller maps the logical address to the
physical address.
16-14 Auxiliary Transmit (ATX) PLL Calibration
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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