Altera Transceiver PHY IP Core - Manual (Page 123)

Signal Name Direction Description
rx_latency_adj_1g[21:0]
Output When you enable 1588, this signal outputs the real
time latency in GMII clock cycles (125 MHz) for the
RX PCS and PMA datapath for 1G mode. Bits 0 to 9
represent fractional number of clock cycles. Bits 10
to 21 represent number of clock cycles.
tx_latency_adj_1g[21:0]
Output When you enable 1588, this signal outputs real time
latency in GMII clock cycles (125 MHz) for the TX
PCS and PMA datapath for 1G mode. Bits 0 to 9
represent fractional number of clock cycles. Bits 10
to 21 represent number of clock cycles.
rx_latency_adj_10g[15:0]
Output When you enable 1588, this signal outputs the real
time latency in XGMII clock cycles (156.25 MHz)
for the RX PCS and PMA datapath for 10G mode.
Bits 0 to 9 represent fractional number of clock
cycles. Bits 10 to 15 represent number of clock
cycles.
tx_latency_adj_10g[15:0]
Output When you enable 1588, this signal outputs real time
latency in XGMII clock cycles (156.25 MHz) for the
TX PCS and PMA datapath for 10G mode. Bits 0 to
9 represent fractional number of clock cycles. Bits
10 to 15 represent number of clock cycles.
rx_data_ready
Output When asserted, indicates that the MAC can begin
sending data to the 10GBASE-KRPHY IP Core.
Register Interface Signals
The Avalon-MM master interface signals provide access to all registers.
Refer to the Typical Slave Read and Write Transfers and Master Transfers sections in the Avalon Memory-
Mapped Interfaces chapter of the Avalon Interface Specifications for timing diagrams.
Table 5-12: Avalon-MM Interface Signals
Signal Name Direction Description
mgmt_clk
Input The clock signal that controls the Avalon-MM PHY
management, interface. If you plan to use the same
clock for the PHY management interface and
transceiver reconfiguration, you must restrict the
frequency range to 100-125 MHz to meet the
specification for the transceiver reconfiguration
clock.
mgmt_clk_reset
Input Resets the PHY management interface. This signal
is active high and level sensitive.
mgmt_addr[7:0]
Input 8-bit Avalon-MM address.
mgmt_writedata[31:0]
Input Input data.
mgmt_readdata[31:0]
Output Output data.
5-14 Register Interface Signals
UG-01080
2015.01.19
Altera Corporation 1G/10 Gbps Ethernet PHY IP Core
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