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Xcvr_gt_rx_dc_gain, Xcvr_rx_dc_gain – Altera Transceiver PHY IP Core User Manual

Page 635

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• BASIC

• CEI

• CPRI

• INTERLAKEN

• PCIE_GEN1

• PCIE_GEN2

• PCIE_GEN3

• QPI

• SFIS

• SONET

• SRIO

• TENG_1588

• TENG_BASER

• TENG_SDI

• XAUI

Assign To

Pin - TX and RX serial data

XCVR_GT_RX_DC_GAIN

Pin Planner and Assignment Editor Name

Receiver Buffer DC Gain Control

Description

Controls the RX buffer DC gain for GTchannels.

Options

• 0-19

8

Assign To

Pin - RX serial data

XCVR_RX_DC_GAIN

Pin Planner and Assignment Editor Name

Receiver Buffer DC Gain Control

Description

Controls the RX buffer DC gain for GX channels.

Options

0 –4

UG-01080

2015.01.19

XCVR_GT_RX_DC_GAIN

19-41

Analog Parameters Set Using QSF Assignments

Altera Corporation

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