Altera Transceiver PHY IP Core - Manual (Page 56)

Note: The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY
IP apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of
Stratix V Native PHY for details.
Related Information
• SDC Timing Constraints of Stratix V Native PHY on page 12-74
This section describes SDC examples and approaches to identify false timing paths.
• About LogicLock Regions
10GBASE-R PHY Simulation Files and Example Testbench
Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II
software creates automatically when you generate your 10GBASE-R PHY IP Core.
Related Information
Running a Simulation Testbench on page 1-6
3-32 10GBASE-R PHY Simulation Files and Example Testbench
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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