Altera Transceiver PHY IP Core - Manual (Page 488)

Table 15-3: PMA Options
Parameter Range Description
Data rate Device
Dependent
Specifies the data rate. The maximum data rate is
12.5 Gbps.
TX local clock division factor 1, 2, 4, 8 Specifies the value of the divider available in the
transceiver channels to divide the input clock to
generate the correct frequencies for the parallel
and serial clocks. This divisor divides the fast
clock from the PLL in nonbonded configurations.
PLL base data rate Device
Dependent
Shows the base data rate of the clock input to the
TX PLL.The PLL base data rate is computed
from the TX local clock division factor
multiplied by the data rate.
Select a PLL base data rate that minimizes the
number of PLLs required to generate all the
clocks for data transmission. By selecting an
appropriate PLL base data rate, you can change
data rates by changing the TX local clock
division factor used by the clock generation
block.
Related Information
• Transceiver Architecture in Cyclone V Devices
• Device Datasheet for Cyclone V Devices
TX PMA Parameters
Note: For more information about PLLs in Cyclone V devices, refer to the Cyclone V PLLs section in
Clock Networks and PLLs in Cyclone V Devices.
Table 15-4: TX PMA Parameters
Parameter Range Description
Enable TX PLL dynamic reconfi‐
guration
On/Off When you turn this option On, you can
dynamically reconfigure the PLL. This option is
also required to simulate TX PLL reconfiguration.
If you turn this option On, the Quartus II Fitter
prevents PLL merging by default; however, you
can specify merging using the
XCVR_TX_PLL_
RECONFIG_GROUP
QSF assignment.
UG-01080
2015.01.19
TX PMA Parameters 15-5
Cyclone V Transceiver Native PHY IP Core Overview Altera Corporation
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