Altera Transceiver PHY IP Core User Manual
Page 40
Signal Name
Direction
Description
rx_data_ready [
Output
When asserted, indicates that the PCS is
sending data to the MAC. Because the
readyLatency
on this Avalon-ST interface is 0,
the MAC must be ready to receive data
whenever this signal is asserted. After
rx_
ready
is asserted indicating the exit from the
reset state, the MAC should store
xgmii_rx_
dc_
in each cycle where
rx_data_
ready
is asserted.
xgmii_rx_clk
Output
This clock is generated by the same reference
clock that is used to generate the transceiver
clock. Its frequency is 156.25 MHz. Use this
clock for the MAC interface to minimize the
size of the FIFO between the MAC and SDR
XGMII RX interface.
rx_coreclkin
Input
When you turn on Create
rx_coreclkin
port,
this signal is available as a 156.25 MHz clock
input port to drive the RX datapath interface
(RX read FIFO).
Serial Interface
rx_serial_data_
Input
Differential high speed serial input data using
the PCML I/O standard. The clock is recovered
from the serial data stream.
tx_serial_data_
Output
Differential high speed serial input data using
the PCML I/O standard. The clock is
embedded from the serial data stream.
Table 3-11: Mapping from XGMII TX Bus to XGMII SDR Bus
Signal Name
XGMII Signal Name
Description
xgmii_tx_dc_[7:0]
xgmii_sdr_data[7:0]
Lane 0 data
xgmii_tx_dc_[8]
xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_tx_dc_[16:9]
xgmii_sdr_data[15:8]
Lane 1 data
xgmii_tx_dc_[17]
xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_tx_dc_[25:18]
xgmii_sdr_data[23:16]
Lane 2 data
xgmii_tx_dc_[26]
xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_tx_dc_[34:27]
xgmii_sdr_data[31:24]
Lane 3 data
xgmii_tx_dc_[35]
xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_tx_dc_[43:36]
xgmii_sdr_data[39:32]
Lane 4 data
3-16
10GBASE-R PHY Data Interfaces
UG-01080
2015.01.19
Altera Corporation
10GBASE-R PHY IP Core