Altera Transceiver PHY IP Core - Manual (Page 125)

Addr Bit R/W Name Description
0xB1 0 RO
SEQ Link Ready
When asserted, the sequencer is indicating that
the link is ready.
Related Information
Avalon Interface Specifications
PMA Registers
The PMA registers allow you to reset the PMA and provide status information.
Table 5-14: PMA Registers - Reset and Status
The following PMA registers allow you to reset the PMA and provide status information.
Addr Bit Access Name Description
0x22 0 RO
pma_tx_pll_is_
locked
Indicates that the TX PLL is locked to the input
reference clock.
0x44
1 RW
reset_tx_
digital
Writing a 1 causes the internal TX digital reset signal
to be asserted. You must write a 0 to clear the reset
condition.
2 RW
reset_rx_analog
Writing a 1 causes the internal RX analog reset signal
to be asserted. You must write a 0 to clear the reset
condition.
3 RW
reset_rx_
digital
Writing a 1 causes the internal RX digital reset signal
to be asserted. You must write a 0 to clear the reset
condition.
0x61 [31:0] RW
phy_serial_
loopback
Writing a 1 puts the channel in serial loopback mode.
0x64 [31:0] RW
pma_rx_set_
locktodata
When set, programs the RX CDR PLL to lock to the
incoming data.
0x65 [31:0] RW
pma_rx_set_
locktoref
When set, programs the RX clock data recovery
(CDR) PLL to lock to the reference clock.
0x66 [31:0] RO
pma_rx_is_
lockedtodata
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode.
0x67 [31:0] RO
pma_rx_is_
lockedtoref
When asserted, indicates that the RX CDR PLL is
locked to the reference clock.
5-16 PMA Registers
UG-01080
2015.01.19
Altera Corporation 1G/10 Gbps Ethernet PHY IP Core
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