Deterministic latency phy analog parameters, Interfaces for deterministic latency phy, Deterministic latency phy analog parameters -15 – Altera Transceiver PHY IP Core User Manual
Page 283: Interfaces for deterministic latency phy -15
Name
Value
Description
Enable channel interface
On/Off
Turn this option on to enable PLL and datapath
dynamic reconfiguration. When you select this
option, the width of
tx_parallel_data
and
rx_
parallel_data
buses increases in the following
way:
• The
rx_parallel_data
bus is 64 bits per lane;
however, only the low-order number of bits
specified by the FPGA fabric transceiver
interface width contain valid data.
• The
tx_parallel_databus
is 44 bits per lane;
however, only the low-order number of bits
specified by the FPGA fabric transceiver
interface width contain valid data for each
lane.
Related Information
Transceiver Reconfiguration Controller PLL Reconfiguration
Deterministic Latency PHY Analog Parameters
This section provides links to describe analog parameters for the Deterministic Latency PHY IP core.
The following links provide information to specify the analog options for your device:
Related Information
•
Analog Settings for Arria V Devices
on page 19-2
•
Analog Settings for Arria V GZ Devices
on page 19-11
•
Analog Settings for Cyclone V Devices
•
Analog Settings for Stratix V Devices
Interfaces for Deterministic Latency PHY
This section describes the top-level signals of the Deterministic Latency PHY IP Core.
The following figure illustrates the top-level signals of the Deterministic Latency PHY IP Core. The
variables in the figure represent the following parameters:
•
•
• — The symbol size
•
—The number of PLLs
UG-01080
2015.01.19
Deterministic Latency PHY Analog Parameters
11-15
Deterministic Latency PHY IP Core
Altera Corporation