Altera Transceiver PHY IP Core - Manual (Page 280)

Name Value Description
Word alignment mode Manual Manual–In this mode, the RX word aligner parses the
incoming data stream for a specific alignment
character. After it identifies this pattern, it shifts the
input stream to align the data and also outputs the
number of bits slipped on
bitslipboundaryse-
lectout[4:0]
for latency compensation on the TX
datapath. This mode is provided for backwards
compatibility with designs implemented in Stratix IV
and Arria II devices.
TX bitslip On/ Off TX bitslip is enabled whenever the word aligner is in
Manual alignment mode. The TX bitslipper uses the
value of
bitslipboundarselect[4:0]
to compensate
for bits slipped on the RX datapath to achieve
deterministic latency.
Enable run length violation
checking
On/ Off If you turn this option on, you can specify the run
length which is the maximum legal number of
contiguous 0s or 1s. This option also creates the rx_
rlv output signal which is asserted when a run length
violation is detected.
Run length 5-160 Specifies the threshold for a run-length violation.
Must be a multiple of 5.
Create optional word aligner
status ports
On/ Off Enable this option to include the
rx_patterndetect
and
rx_syncstatus
ports.
Create optional 8B/10B control
and status ports
On/ Off Enable this option to include the 8B/10B
rx_
runningdisp
,
rx_errdetect
, and
rx_disperr
signals at the top level of the Deterministic Latency
PHY IP Core.
Create PMA optional status
ports
On/ Off Enable this option to include the 8B/10B
rx_is_
lockedtoref
,
rx_is_lockedtodata
, and
rx_
signaldetect
signals at the top level of the
Deterministic Latency PHY IP Core.
Avalon data interfaces On/ Off This option is typically required if you are planning to
import your Deterministic Latency PHY IP Core into
a Qsys system.
11-12 Additional Options Parameters for Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation Deterministic Latency PHY IP Core
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