Altera Transceiver PHY IP Core - Manual (Page 232)

Interfaces
Figure 9-2: Custom PHY Top-Level Signals
The variables in Figure 9–2 represent the following parameters:
• —The number of lanes
• —The width of the FPGA fabric to transceiver interface per lane
• — The symbol size
•
—The number of PLLs
Figure 9-3: Custom PHY Interfaces
tx_parallel_data[< n>-1>:0]
tx_clkout
tx_datak[(/)-1:0]
tx_forcedisp[< n>(/)-1:0]
tx_dispval[< n>(/)-1:0]
rx_parallel_data[< n>-1:0]
rx_clkout[-1:0]
rx_datak[(/)-1:0]
rx_runningdisp[ (/)-1:0]
rx_enabyteord[< n>-1:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
rx_coreclkin[< n>-1:0]
tx_coreclkin[< n>-1:0]
Custom PHY Top-Level Signals
tx_serial_data[< n>-1:0]
rx_serial_data[< n>-1:0]
tx_ready
rx_ready
pll_locked[
-1:0]
tx_forceelecidle[< n>-1:0]
tx_bitslipboundaryselect[ 5-1:0]
rx_disperr[ (/)-1:0]
rx_errdetect[ (/)-1:0]
rx_syncstatus[ (/) -1:0]
rx_is_lockedtoref[< n>-1:0]
rx_is_lockedtodata[< n>-1:0]
rx_signaldetect[< n>-1:0]
rx_bitslip [-1:0]
rx_bitslipboundaryselectout[ 5-1:0]
rx_patterndetect[< n>(/)-1:0]
rx_rmfifodatainserted[< n>-1:0]
rx_rmfifodatadeleted[< n>-1:0]
rx_rlv[-1:0]
rx_recovered_clk[ -1:0]
rx_byteordflag[ -1:0]
pll_powerdown
tx_digitalreset[< n>-1:0]
tx_analogreset[< n>-1:0]
tx_cal_busy[< n>-1:0]
rx_digitalreset[< n>-1:0]
rx_analogreset[< n>-1:0]
rx_cal_busy[< n>-1:0]
reconfig_to_xcvr[( 70-1):0]
reconfig_from_xcvr[( 46-1):0]
Avalon-ST Tx
from MAC
Speed
Serial I/O
Avalon-MM PHY
Management
Interface
Clocks
Optional
Optional
Status
(Optional)
Avalon-ST Rx
to MAC
Transceiver
Reconfiguration
Interface
Optional
Reset Control
and Status
(Optional)
Note: By default block diagram shown in the MegaWizard Plug-In Manager labels the external pins with
the interface type and places the interface name inside the box. The interface type and name are
used in the _hw.tcl file that describes the component. If you turn on Show signals, the block
diagram displays all top-level signal names.
Related Information
Component Interface Tcl Reference
Data Interfaces
This topic describes the Avalon-ST TX and RX interface signals as well as the serial interface and status
signals.
UG-01080
2015.01.19
Interfaces 9-19
Custom PHY IP Core Altera Corporation
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