Altera Transceiver PHY IP Core - Manual (Page 473)

Name Dir Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
tx_10g_data_valid
[-1:0]
Input Yes
When asserted, indicates if
tx_data
is valid Use of
this signal depends upon the protocol you are
implementing, as follows:
• 10G BASE-R: Tie to 1'b1
• Interlaken: Acts as control for FIFO write
enable. You should tie this signal to
tx_10g_
fifo_pempty
.
• Basic with phase compensation FIFO: Tie to
1'b1 as long as
tx_coreclkin = data_rate/
pld_pcs interface width
. Otherwise, tie this
signal to
tx_10g_fifo_pempty.
• Basic with phase compensation FIFO in register
mode. This mode only allows a 1:1 gear box
ratio such as 32:32 and 64:64; consequently,
you can tie
tx_10g_data_valid
to 1’b1.
tx_10g_fifo_full
[-1:0]
Output Yes When asserted, indicates that the TX FIFO is full.
Synchronous to
tx_std_clkout
,
tx_10g_fifo_pfull
[-1:0]
Output Yes When asserted, indicates that the TX FIFO is
partially full.
tx_10g_fifo_empty
[-1:0]
Output No TX FIFO empty flag. Synchronous to
tx_std_
clkout
. This signal is pulse-stretched; you must
use a synchronizer.
tx_10g_fifo_pempty
[-1:0]
Output No TX FIFO partially empty flag. Synchronous to
tx_
std_clkout
. This signal is pulse-stretched; you
must use a synchronizer.
tx_10g_fifo_del
[-1:0]
Output Yes When asserted, indicates that a word has been
deleted from the rate match FIFO. This signal is
used for the 10GBASE-R protocol.
tx_10g_fifo_insert
[-1:0]
Output No When asserted, indicates that a word has been
inserted into the rate match FIFO. This signal is
used for the 10GBASE-R protocol. This signal is
pulse-stretched, you must use a synchronizer.
RX FIFO
14-62 10G PCS Interface
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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