Logical lane assignment restriction, Xaui phy dynamic reconfiguration interface signals, Logical lane assignment restriction -26 – Altera Transceiver PHY IP Core User Manual
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Example 6-2: Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 8 reconfiguration interfaces for connection to the
external reconfiguration controller.Reconfiguration interface offsets 0-3
are connected to the transceiver channels.Reconfiguration interface offsets
4-7 are connected to the transmit PLLs.
Although you must initially create a separate reconfiguration interface for each channel and TX PLL in
your design, when the Quartus II software compiles your design, it reduces the number of reconfiguration
interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfigura‐
tion interface for at least three channels because three channels share an Avalon-MM slave interface
which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect
the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration
Controller IP Cores. Doing so causes a Fitter error. For more information, refer to “Transceiver Reconfi‐
guration Controller to PHY IP Connectivity”.
Related Information
•
Transceiver Reconfiguration Controller to PHY IP Connectivity
•
Transceiver Reconfiguration Controller IP Core Overview
Logical Lane Assignment Restriction
If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that you assign the
starting channel number.
Logical channel 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver
bank. However, if you have already created a PCB with a different lane assignment for logical lane 0, you
can use the workaround shown in the following example to remove this restriction. This redefines the
pma_bonding_master
parameter using the Quartus II Assignment Editor. In this example, the
pma_bonding_master
was originally assigned to physical channel 1. (The original assignment could also
have been to physical channel 4.) The to parameter reassigns the
pma_bonding_master
to the PHY IP
instance name. You must substitute the instance name from your design for the instance name shown in
quotation marks
Example 6-3: Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V
Devices for ×6 or ×N Bonding
set_parameter -name pma_bonding_master "\"1\"" -to "<PHY IP instance name>"
Related Information
•
Transceiver Reconfiguration Controller to PHY IP Connectivity
•
Transceiver Reconfiguration Controller IP Core Overview
XAUI PHY Dynamic Reconfiguration Interface Signals
This section describes the signals in the reconfiguration interface. This interface uses the Avalon-MM
PHY Management interface clock.
6-26
Logical Lane Assignment Restriction
UG-01080
2015.01.19
Altera Corporation
XAUI PHY IP Core