Altera Transceiver PHY IP Core User Manual
Page 341
Test Enable
bits. The following table lists the offsets and registers of the pattern generators and verifiers
in the 10G PCS.
Note: The 10G PRBS generator inverts its pattern before transmission. The 10G PRBS verifier inverts the
received pattern before verification. You may need to invert the patterns if you connect to third-
party PRBS pattern generators and checkers.
Note: Note: All undefined register bits are reserved.
Table 12-36: Pattern Generator Registers
Offset
Bits
R/W
Name
Description
0x12D
[15:0]
R/W
Seed A for PRP
Bits [15:0] of seed A for the pseudo-
random pattern.
0x12E
[15:0]
Bits [31:16] of seed A for the pseudo-
random pattern.
0x12F
[15:0]
Bits [47:21] of seed A for the pseudo-
random pattern.
0x130
[9:0]
Bits [57:48] of seed A for the pseudo-
random pattern.
0x131
[15:0]
R/W
Seed B for PRP
Bits [15:0] of seed B for the pseudo-
random pattern.
0x132
[15:0]
Bits [31:16] of seed B for the pseudo-
random pattern.
0x133
[15:0]
Bits [47:32] of seed B for the pseudo-
random pattern.
0x134
[9:0]
Bits [57:48] of seed B for the pseudo-
random pattern.
UG-01080
2015.01.19
10G PCS Pattern Generators
12-43
Stratix V Transceiver Native PHY IP Core
Altera Corporation