1g/10gbe phy interfaces, 1g/10gbe phy interfaces -7 – Altera Transceiver PHY IP Core User Manual
Page 116
1G/10GbE PHY Interfaces
Figure 5-2: 1G/10GbE PHY Top-Level Signals
xgmii_tx_dc[71:0]
xgmii_tx_clk
xgmii_rx_dc[71:0]
xgmii_rx_clk
gmii_tx_d[7:0]
gmii_rx_d[7:0]
gmii_tx_en
gmii_tx_err
gmii_rx_err
gmii_rx_dv
led_char_err
led_link
led_disp_err
led_an
mgmt_clk
mgmt_clk_reset
mgmt_address[7:0]
mgmt_writedata[31:0]
mgmt_readdata[31:0]
mgmt_write
mgmt_read
mgmt_waitrequest
rx_recovered_clk
tx_clkout_1g
rx_clkout_1g
rx_coreclkin_1g
tx_coreclkin_1g
pll_ref_clk_1g
pll_ref_clk_10g
pll_powerdown_1g
pll_powerdown_10g
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
usr_seq_reset
1G/10GbE Top-Level Signals
Reconfiguration
rx_serial_data
tx_serial_data
reconfig_to_xcvr[(
reconfig_from_xcvr[(
rc_busy
lt_start_rc
main_rc[5:0]
post_rc[4:0]
pre_rc[3:0]
tap_to_upd[2:0]
seq_start_rc
pcs_mode_rc[5:0]
mode_1g_10gbar
en_lcl_rxeq
rxeq_done
rx_block_lock
rx_hi_ber
pll_locked
rx_is_lockedtodata
tx_cal_busy
rx_cal_busy
calc_clk_1g
rx_syncstatus
tx_pcfifo_error_1g
rx_pcfifo_error_1g
lcl_rf
tm_in_trigger[3:0]
tm_out_trigger[3:0]
rx_rlv
rx_clkslip
rx_latency_adj_1g[21:0]
tx_latency_adj_1g[21:0]
rx_latency_adj_10g[15:0]
tx_latency_adj_10g[15:0]
rx_data_ready
Transceiver
Serial Data
XGMII
and GMII
Interfaces
Avalon-MM PHY
Management
Interface
Clocks and
Reset
Interface
Status
The block diagram shown in the GUI labels the external pins with the interface type and places the
interface name inside the box. The interface type and name are used in the _hw.tcl file. If you turn on
Show signals, the block diagram displays all top-level signal names. For more information about _hw.tcl
files, refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II
Handbook
Note: Some of the signals shown in are this figure are unused and will be removed in a future release. The
descriptions of these identifies them as not functional.
Related Information
UG-01080
2015.01.19
1G/10GbE PHY Interfaces
5-7
1G/10 Gbps Ethernet PHY IP Core
Altera Corporation