Altera Transceiver PHY IP Core - Manual (Page 240)

Signal Name Direction Description
tx_cal_busy[-1:0]
Output When asserted, indicates that the initial TX
calibration is in progress. It is also asserted if
reconfiguration controller is reset. It will not be
asserted if you manually re-trigger the calibration
IP. You must hold the channel in reset until
calibration completes.
rx_digitalreset[-1:0]
Input When asserted, resets the RX PCS.
rx_analogreset[-1:0]
Input When asserted, resets the RX CDR.
rx_cal_busy[-1:0]
Output When asserted, indicates that the initial RX
calibration is in progress. It is also asserted if
reconfiguration controller is reset. It will not be
asserted if you manually re-trigger the calibration
IP.
Related Information
• Timing Constraints for Bonded PCS and PMA Channels on page 17-10
• Transceiver Reset Control in Stratix V Devices
• Transceiver Reset Control in Arria V Devices
• Transceiver Reset Control in Cyclone V Devices
Register Interface and Register Descriptions
The Avalon-MM PHY management interface provides access to the Custom PHY PCS and PMA
registers, resets, error handling, and serial loopback controls. You can use an embedded controller acting
as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface.
UG-01080
2015.01.19
Register Interface and Register Descriptions 9-27
Custom PHY IP Core Altera Corporation
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