Altera Transceiver PHY IP Core - Manual (Page 241)

Figure 9-4: Custom PHY IP Core
System
Interconnect
Fabric
to Embedded
Controller
Custom PHY PCS and PMA
Custom PHY IP Core
Resets
Status
Control S
Avalon-MM
Control
S
Avalon-MM
Status
Reset
Controller
PLL
Reset
Clocks Clocks
to
Transceiver
Reconfiguration
Controller
Tx Data Tx Parallel Data
Rx Data Rx Parallel Data
M
Avalon-MM
PHY
Mgmt
S
Rx Serial Data & Status
Reconfig to and from Transceiver
Tx Serial Data
PMA and PCS
Registers
.
.
.
Table 9-20: Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk
Input Avalon-MM clock input. There is no
frequency restriction for the
phy_
mgmt_clk
; however, if you plan to use
the same clock for the PHY
management interface and
transceiver reconfiguration, you must
restrict the frequency range of
phy_
mgmt_clk
to 100-150 MHz to meet
the specification for the transceiver
reconfiguration clock.
phy_mgmt_clk_reset
Input Global reset signal. This signal is
active high and level sensitive.
phy_mgmt_address[8:0]
Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input Input data.
9-28 Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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