Altera Transceiver PHY IP Core User Manual
Page 519
Area
Feature
Stratix V
Arria V
Arria V GZ
Cyclone V
Transceiver
Channel/PLL
Reconfiguration
RX CDR reconfiguration
Yes
Yes
Yes
Yes
Reconfiguration of PCS blocks
Yes
Yes
Yes
Yes
TX PLL switching
Yes
Yes
Yes
Yes
ATX PLL switching
Yes
—
Yes
—
TX local clock divider
reconfiguration (1,2,4,8)
Yes
Yes
Yes
Yes
FPGA fabric-transceiver channel
data width reconfiguration
Yes
Yes
Yes
Yes
For more information about the features that are available for each device refer to the following device
documentation: Dynamic Reconfiguration in Stratix V Devices, Dynamic Reconfiguration in Arria V
Devices, and Dynamic Reconfiguration in Cyclone V Devices. These chapters are included in the Stratix V,
Arria V, and Cyclone V device handbooks, respectively.
Related Information
•
•
•
Transceiver Reconfiguration Controller System Overview
This section describes the Transceiver Reconfiguration Controller’s role. You can include the embedded
controller that initiates reconfiguration in your FPGA or use an embedded processor on the PCB.
16-2
Transceiver Reconfiguration Controller System Overview
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview