Altera Transceiver PHY IP Core - Manual (Page 105)

Table 4-22: PCS Registers
Addr Bit Acce
ss
Name Description
0x80 31:0 RW
Indirect_addr
Because the PHY implements a single channel, this
register must remain at the default value of 0 to specify
logical channel 0.
0x81
2 RW
RCLR_ERRBLK_CNT
Error Block Counter clear register. When set to 1, clears
the
RCLR_ERRBLK_CNT
register. When set to 0, normal
operation continues.
3 RW
RCLR_BER_COUNT
BER Counter clear register. When set to 1, clears the
RCLR_BER_COUNT
register. When set to 0, normal
operation continues.
0x82
1 RO
HI_BER
High BER status. When set to 1, the PCS is reporting a
high BER. When set to 0, the PCS is not reporting a high
BER.
2 RO
BLOCK_LOCK
Block lock status. When set to 1, the PCS is locked to
received blocks. When set to 0, the PCS is not locked to
received blocks.
3 RO
TX_FULL
When set to 1, the
TX_FIFO
is full.
4 RO
RX_FULL
When set to 1, the
RX_FIFO
is full.
5 RO
RX_SYNC_HEAD_ERROR
When set to 1, indicates an RX synchronization error.
6 RO
RX_SCRAMBLER_ERROR
When set to 1, indicates an RX scrambler error.
7 RO
Rx_DATA_READY
When set to 1, indicates the PHY is ready to receive data.
Creating a 10GBASE-KR Design
Here are the steps you must take to create a 10GBASE-KR design using this PHY.
1. Generate the 10GBASE-KR PHY with the required parameterization.
2. Generate a Transceiver Reconfiguration Controller with the correct number of reconfiguration
interfaces based on the number of channels you are using. This controller is connected to all the
transceiver channels. It implements the reconfiguration process.
3. Generate a Transceiver Reset Controller.
4. Create arbitration logic that prioritizes simultaneous reconfiguration requests from multiple channels.
This logic should also acknowledge the channel being serviced causing the requestor to deassert its
request signal.
5. Create a state machine that controls the reconfiguration process. The state machine should:
a. Receive the prioritized reconfiguration request from the arbiter
b. Put the Transceiver Reconfiguration Controller into MIF streaming mode.
c. Select the correct MIF and stream it into the appropriate channel.
d. Wait for the reconfiguration process to end and provide status signal to arbiter.
6. Generate one ROM for each required configuration.
UG-01080
2015.01.19
Creating a 10GBASE-KR Design 4-49
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option Altera Corporation
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