Altera Transceiver PHY IP Core - Manual (Page 8)

Bit Reversal and Polarity Inversion...........................................................................................13-20
Interfaces...................................................................................................................................................13-23
Common Interface Ports............................................................................................................ 13-23
Standard PCS Interface Ports.....................................................................................................13-29
SDC Timing Constraints........................................................................................................................ 13-34
Dynamic Reconfiguration...................................................................................................................... 13-35
Simulation Support..................................................................................................................................13-36
Arria V GZ Transceiver Native PHY IP Core...................................................14-1
Device Family Support for Arria V GZ Native PHY............................................................................ 14-2
Performance and Resource Utilization for Arria V GZ Native PHY................................................. 14-3
Parameter Presets.......................................................................................................................................14-3
Parameterizing the Arria V GZ Native PHY......................................................................................... 14-3
General Parameters for Arria V GZ Native PHY .....................................................................14-4
PMA Parameters for Arria V GZ Native PHY.......................................................................... 14-6
Standard PCS Parameters for the Native PHY........................................................................14-13
10G PCS Parameters for Arria V GZ Native PHY .................................................................14-29
Interfaces for Arria V GZ Native PHY ................................................................................................ 14-46
Common Interface Ports for Arria V GZ Native PHY...........................................................14-46
Standard PCS Interface Ports.....................................................................................................14-53
10G PCS Interface........................................................................................................................14-58
SDC Timing Constraints of Arria V GZ Native PHY ....................................................................... 14-70
Dynamic Reconfiguration for Arria V GZ Native PHY.....................................................................14-71
Simulation Support..................................................................................................................................14-72
Cyclone V Transceiver Native PHY IP Core Overview.................................... 15-1
Cyclone Device Family Support...............................................................................................................15-2
Cyclone V Native PHY Performance and Resource Utilization......................................................... 15-2
Parameterizing the Cyclone V Native PHY........................................................................................... 15-2
General Parameters....................................................................................................................................15-3
PMA Parameters........................................................................................................................................15-4
TX PMA Parameters..................................................................................................................... 15-5
TX PLL Parameters........................................................................................................................15-6
RX PMA Parameters..................................................................................................................... 15-7
Standard PCS Parameters.........................................................................................................................15-9
Phase Compensation FIFO.........................................................................................................15-11
Byte Ordering Block Parameters............................................................................................... 15-12
Byte Serializer and Deserializer..................................................................................................15-14
8B/10B........................................................................................................................................... 15-14
Rate Match FIFO..........................................................................................................................15-15
Word Aligner and BitSlip Parameters...................................................................................... 15-18
Bit Reversal and Polarity Inversion...........................................................................................15-20
Interfaces...................................................................................................................................................15-22
Common Interface Ports............................................................................................................ 15-22
Cyclone V Standard PCS Interface Ports................................................................................. 15-28
SDC Timing Constraints........................................................................................................................ 15-32
Dynamic Reconfiguration...................................................................................................................... 15-33
TOC-8 Altera Transceiver PHY IP Core User Guide
Altera Corporation