Altera Transceiver PHY IP Core User Manual
Page 491
Table 15-6: RX PMA Parameters
Parameter
Range
Description
Enable CDR dynamic reconfigura‐
tion
On/Off
When you turn this option On, you can
dynamically change the data rate of the CDR
circuit.
Number of CDR reference clocks
1–5
Specifies the number of reference clocks for the
CDRs.
Selected CDR reference clock
0–4
Specifies the index of the selected CDR reference
clock.
Selected CDR reference clock
frequency
Device
Dependent
Specifies the frequency of the clock input to the
CDR.
PPM detector threshold
+/- 1000 PPM Specifies the maximum PPM difference the CDR
can tolerate between the input reference clock
and the recovered clock.
Enable rx_pma_clkout port
On/Off
When you turn this option On, the RX parallel
clock which is recovered from the serial received
data is an output of the PMA.
Enable rx_is_lockedtodata port
On/Off
When you turn this option On, the
rx_is_
lockedtodata
port is an output of the PMA.
Enable rx_is_lockedtoref port
On/Off
When you turn this option On, the
rx_is_
lockedtoref
port is an output of the PMA.
Enable rx_set_lockedtodata and
rx_set_locktoref ports
On/Off
When you turn this option On, the
rx_set_
lockedtdata
and
rx_set_lockedtoref
ports are
outputs of the PMA.
Enable rx_pma_bitslip_port
On/Off
When you turn this option On, the
rx_pma_
bitslip
is an input to the core. The deserializer
slips one clock edge each time this signal is
asserted. You can use this feature to minimize
uncertainty in the serialization process as
required by protocols that require a datapath with
deterministic latency such as CPRI.
Enable rx_seriallpbken port
On/Off
When you turn this option On, the
rx_
seriallpbken
is an input to the core. When your
drive a 1 on this input port, the PMA operates in
serial loopback mode with TX data looped back
to the RX channel.
Related Information
15-8
RX PMA Parameters
UG-01080
2015.01.19
Altera Corporation
Cyclone V Transceiver Native PHY IP Core Overview