Altera Transceiver PHY IP Core - Manual (Page 121)

Table 5-9: RX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name XGMII Signal Name Description
xgmii_rx_dc[7:0] xgmii_sdr_data[7:0]
Lane 0 data
xgmii_rx_dc[8] xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_rx_dc[16:9] xgmii_sdr_data[15:8]
Lane 1 data
xgmii_rx_dc[17] xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_rx_dc[25:18] xgmii_sdr_data[23:16]
Lane 2 data
xgmii_rx_dc[26] xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_rx_dc[34:27] xgmii_sdr_data[31:24]
Lane 3 data
xgmii_rx_dc[35] xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_rx_dc[43:36] xgmii_sdr_data[39:32]
Lane 4 data
xgmii_rx_dc[44] xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_rx_dc[52:45] xgmii_sdr_data[47:40]
Lane 5 data
xgmii_rx_dc[53] xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_rx_dc[61:54] xgmii_sdr_data[55:48]
Lane 6 data
xgmii_rx_dc[62] xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_rx_dc[70:63] xgmii_sdr_data[63:56]
Lane 7 data
xgmii_rx_dc[71] xgmii_sdr_ctrl[7]
Lane 7 control
Serial Data Interface
Table 5-10: Serial Data Signals
Signal Name Direction Description
rx_serial_data
Input RX serial input data
tx_serial_data
Output TX serial output data
1G/10GbE Control and Status Interfaces
The 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY.
Table 5-11: Control and Status Signals
Signal Name Direction Description
rx_block_lock
Output Asserted to indicate that the block synchronizer has
established synchronization.
5-12 Serial Data Interface
UG-01080
2015.01.19
Altera Corporation 1G/10 Gbps Ethernet PHY IP Core
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