Transceiver reconfiguration controller interfaces – Altera Transceiver PHY IP Core User Manual
Page 525
Name
Value
Description
Enable PLL reconfiguration
support block
On/Off
When enabled, the Transceiver Reconfigura‐
tion Controller includes logic to perform PLL
reconfiguration.
Transceiver Reconfiguration Controller Interfaces
This section describes the top-level signals of the Transceiver Reconfiguration Controller.
Figure 16-2: Top-Level Signals of the Transceiver Reconfiguration Controller
Transceiver Reconfiguration Controller Top-Level Signals
Reconfiguration
Management
Avalon-MM Slave
Interface
MIF Reconfiguration
Avalon-MM Master
Interface
Transceiver
Reconfiguration
reconfig_mif_address[31:0]
reconfig_mif_read
reconfig_mif_readdata[15:0]
reconfig_mif_waitrequest
cal_busy_in
mgmt_clk_clk
mgmt_rst_reset
reconfig_mgmt_address[6:0]
reconfig_mgmt_writedata[31:0]
reconfig_mgmt_readdata[31:0]
reconfig_mgmt_write
reconfig_mgmt_read
reconfig_mgmt_waitrequest
reconfig_to_xcvr[(
reconfig_from_xcvr[(
reconfig_busy
tx_cal_busy
rx_cal_busy
Note: By default, the Block Diagram shown in the MegaWizard Plug-In Manager labels the external pins
with the interface type and places the interface name inside the box. The interface type and name
are used in the Hardware Component Description File (_hw.tcl). If you click Show signals, the
block diagram expands to show all of the signals of the component given the options currently
selected in the MegaWizard Plug-In Manager.
For more information about _hw.tcl files refer to the Component Interface Tcl Reference in volume 1 of
the Quartus II Handbook.
Related Information
MIF Reconfiguration Management Avalon-MM Master Interface
This section describes the signals that comprise of the MIF Reconfiguration Management Interface. The
Transceiver Reconfiguration Controller communicates to an on-chip ROM or any other memory used to
store the MIF using this interface.
Table 16-5: MIF Reconfiguration Management Avalon-MM Master Interface
Signal Name
Direction
Description
reconfig_mif_address[31:0]
Output
This is the Avalon-MM address. This is a byte
address.
16-8
Transceiver Reconfiguration Controller Interfaces
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview