Altera Transceiver PHY IP Core User Manual
Page 652
Stratix IV GX Devices
(20)
Stratix V Devices
Signal Name
Width
Signal Name
Width
cal_blk_powerdown
—
Not available
—
rx_syncstatus
[2<n> -1:0]
rx_syncstatus
[<n> *2 -1:0]
rx_patterndetect
[2<n> -1:0]
Not available
—
rx_invpolarity
[2<n> -1:0]
Not available
—
rx_ctrldetect
[2<n> -1:0]
Not available
—
rx_errdetect
[2<n> -1:0]
rx_errdetect
[<n> *2 -1:0]
rx_disperr
[2<n> -1:0]
rx_disperr
[<n> *2 -1:0]
tx_invpolarity
[2<n> -1:0]
Not available
—
rx_runningdisp
[2<n> -1:0]
Not available
—
rx_rmfifofull
[2<n> -1:0]
Not available
—
rx_rmfifoempty
[2<n> -1:0]
Not available
—
rx_rmfifodatainserted
[2<n> -1:0]
Not available
—
rx_rmfifodatadeleted
[2<n> -1:0]
Not available
—
Transceiver Reconfiguration
cal_blk_clk
1
These signals are
included in the
reconfig_to_xcvr
bus.
—
reconfig_clk
1
—
reconfig_togxb
[3:0]
reconfig_to_xcvr
Variable
reconfig_fromgxb
[16:0]
reconfig_from_xcvr
Variable
Avalon MM Management Interface
Not Available
—
phy_mgmt_clk_rst
1
phy_mgmt_clk
1
phy_mgmt_address
[8:0]
phy_mgmt_read
1
phy_mgmt_readdata
[31:0]
phy_mgmt_write
1
phy_mgmt_writedat
[31:0]
(20)
<n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
20-6
Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices
UG-01080
2013.12.20
Altera Corporation
Migrating from Stratix IV to Stratix V Devices Overview