Altera Transceiver PHY IP Core - Manual (Page 18)

Figure 1-3: Directory Structure for Generated Files
_sim/synopsys -
Simulation files for Synopsys simulation tools
/ - includes PHY IP Verilog HDL and
SystemVerilog design files for synthesis
. v or .vhd - the parameterized transceiver PHY IP core
.qip - lists all files used in the transceiver PHY IP design
.bsf - a block symbol file for you transceiver PHY IP core
_sim/altera_xcvr - includes plain text
files that describe all necessary files required for a successful simulation. The
plain text files contain the names of all required files and the correct order
for reading these files into your simulation tool.
_sim/aldec -
Simulation files for Riviera-PRO simulation tools
_sim/cadence -
Simulation files for Cadence simulation tools
_sim/mentor -
Simulation files for Mentor simulation tools
The following table describes the key files and directories for the parameterized transceiver PHY IP core
and the simulation environment which are in clear text.
Table 1-2: Transceiver PHY Files and Directories
File Name Description
The top-level project directory.
.v or .vhd The top-level design file.
.qip A list of all files necessary for Quartus II compila‐
tion.
.bsf A Block Symbol File (.bsf) for your transceiver
PHY.
// The directory that stores the HDL files that define
the protocol-specific PHY IP core. These files are
used for synthesis.
UG-01080
2015.01.19
Running a Simulation Testbench 1-7
Introduction to the Protocol-Specific and Native Transceiver PHYs Altera Corporation
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