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Altera Transceiver PHY IP Core User Manual

Page 333

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Parameter

Range

Description

Enable rx_10g_fifo_rd_en port

(Interlaken)

On/Off

When you turn this option On, the 10G

PCS includes the

rx_10g_fifo_rd_en

input port. Asserting this signal reads a

word from the RX FIFO. This signal is

only available for the Interlaken

protocol.

Enable rx_10g_fifo_align_val port

(Interlaken)

On/Off

When you turn this option On, the 10G

PCS includes the

rx_10g_fifo_align_

val

output port. This signal is asserted

when the word alignment pattern is

found. This signal is only available for

the Interlaken protocol.

enable rx10g_clk33out port

On/Off

When you turn this option On, the 10G

PCS includes a divide by 33 clock output

port. You typically need this option

when the fabric to PCS interface width

is 66.

Enable rx_10g_fifo_align_clr port

(Interlaken)

On/Off

When you turn this option On, the 10G

PCS includes the

rx_10g_fifo_align_

clr

input port. When this signal is

asserted, the FIFO resets and begins

searching for a new alignment pattern.

This signal is only available for the

Interlaken protocol.

Enable rx_10g_fifo_align_en port

(Interlaken)

On/Off

When you turn this option On, the 10G

PCS includes the

rx_10g_fifo_align_

en

input port. This signal is used for

FIFO deskew for Interlaken. When

asserted, the corresponding channel is

enabled for alignment. This signal is

only available for the Interlaken

protocol.

Interlaken Frame Generator

TX Frame generator generates the metaframe. It encapsulates the payload from MAC with the framing

layer control words, including sync, scrambler, skip and diagnostic words. The following table describes

the Interlaken frame generator parameters.

Table 12-26: Interlaken Frame Generator Parameters

Parameter

Range

Description

teng_tx_framgen_enable

On/Off

When you turn this option On, the

frame generator block of the 10G PCS is

enabled.

teng_tx_framgen_user_length

0-8192

Specifies the metaframe length.

UG-01080

2015.01.19

10G PCS Parameters for Stratix V Native PHY

12-35

Stratix V Transceiver Native PHY IP Core

Altera Corporation

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