Altera Transceiver PHY IP Core - Manual (Page 223)

reference clock frequency is greater than the local receiver reference clock frequency. It inserts SKP
symbols or ordered-sets when the local receiver reference clock frequency is greater than the upstream
transmitter reference clock frequency.
If you enable the rate match FIFO, the MegaWizard Plug-In Manager provides options to enter the rate
match insertion and deletion patterns. The lower 10 bits are the control pattern, and the upper 10 bits are
the skip pattern.
Table 9-7: Rate Match FIFO Options
Name Value Description
Enable rate match FIFO On/Off Turn this option on, to enable the
rate match functionality. Turning this
option on adds the
rx_rmfifoda-
tainserted
, and
rx_rmfifodatade-
leted
status signals to your PHY.
Rate match insertion/deletion +ve
disparity pattern
1101000011
1010000011
Enter a 10-bit skip pattern (bits 10-
19) and a 10-bit control pattern (bits
0-9). The skip pattern must have
neutral disparity.
Rate match insertion/deletion -ve
disparity pattern
0010111100
0101111100
Enter a 10-bit skip pattern (bits 10-
19) and a 10-bit control pattern (bits
0-9). The skip pattern must have
neutral disparity.
Create optional rate match FIFO
status ports
On/Off When enabled, creates the
rx_
rmfifoddatainserted
and
rx_
rmfifodatadeleted
signals from the
rate match FIFO become output
ports.
Note: If you have the auto-negotiation state machine in your transceiver design, please note that the rate
match FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets
during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered
sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base
Support Solution .
8B/10B Encoder and Decoder Parameters
The 8B/10B encoder generates 10-bit code groups (control or data word) with proper disparity from the
8-bit data and 1-bit control identifier. The 8B/10B decoder receives 10-bit data from the rate matcher and
decodes it into an 8-bit data and 1-bit control identifier.
9-10 8B/10B Encoder and Decoder Parameters
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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