Altera Transceiver PHY IP Core - Manual (Page 390)

Table 13-13: Byte Serializer and Deserializer Parameters
Parameter Range Description
Enable TX byte serializer On/Off When you turn this option On, the PCS includes a TX
byte serializer which allows the PCS to run at a lower
clock frequency to accommodate a wider range of FPGA
interface widths.
Enable RX byte deserial‐
izer
On/Off When you turn this option On, the PCS includes an RX
byte deserializer which allows the PCS to run at a lower
clock frequency to accommodate a wider range of FPGA
interface widths.
Related Information
Transceiver Architecture in Arria V Devices
8B/10B
The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier.
In 8-bit width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or
data word) with proper disparity. The 8B/10B decoder decodes the data into an 8-bit data and 1-bit
control identifier.
Note: For more information refer to the 8B/10B Encoder and 8B/10B Decoder sections in the Transceiver
Architecture in Arria V Devices.
Table 13-14: 8B/10B Encoder and Decoder Parameters
Parameter Range Description
Enable TX 8B/10B
encoder
On/Off When you turn this option On, the PCS includes the 8B/
10B encoder.
Enable TX 8B/10B
disparity control
On/Off When you turn this option On, the PCS includes
disparity control for the 8B/10B encoder. You force the
disparity of the 8B/10B encoder using the
tx_forcedisp
and
tx_dispval
control signal.
Enable RX 8B/10B
decoder
On/Off When you turn this option On, the PCS includes the 8B/
10B decoder.
Related Information
Transceiver Architecture in Arria V Devices
Rate Match FIFO
The rate match FIFO compensates for the very small frequency differences between the local system clock
and the RX recovered clock.
For more information refer to the Rate Match FIFO sections in the Transceiver Architecture in Arria V
Devices.
UG-01080
2015.01.19
8B/10B 13-15
Arria V Transceiver Native PHY IP Core Altera Corporation
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