Altera Transceiver PHY IP Core - Manual (Page 508)

Name Direction Description
TX and RX serial ports
tx_serial_data[-1:0] Output TX differential serial output data.
rx_serial_data[-1:0] Input RX differential serial output data.
Control and Status ports
rx_seriallpbken[-1:0] Input When asserted, the transceiver enters
serial loopback mode. Loopback drives
serial TX data to the RX interface.
rx_set_locktodata[-1:0] Input When asserted, programs the RX CDR to
manual lock to data mode in which you
control the reset sequence using the
rx_
set_locktoref
and
rx_set_
locktodata
. Refer to “Transceiver Reset
Sequence” in Transceiver Reset Control
in Cyclone V Devices for more informa‐
tion about manual control of the reset
sequence.
rx_set_locktoref[-1:0] Input When asserted, programs the RX CDR to
manual lock to reference mode in which
you control the reset sequence using the
rx_set_locktoref
and
rx_set_
locktodata
. Refer to Refer to
“Transceiver Reset Sequence” in
Transceiver Reset Control in CycloneV
Devices for more information about
manual control of the reset sequence.
pll_locked[
-1:0]
Output When asserted, indicates that the PLL is
locked to the input reference clock.
rx_is_lockedtodata[-1:0] Output When asserted, the CDR is locked to the
incoming data.
rx_is_lockedtoref[-1:0] Output When asserted, the CDR is locked to the
incoming reference clock.
UG-01080
2015.01.19
Common Interface Ports 15-25
Cyclone V Transceiver Native PHY IP Core Overview Altera Corporation
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