Altera Transceiver PHY IP Core - Manual (Page 104)

Addr Bit Access Name Description
0x64 [31:0] RW
pma_rx_set_
locktodata
When set, programs the RX CDR PLL to lock to the
incoming data.
0x65 [31:0] RW
pma_rx_set_
locktoref
When set, programs the RX clock data recovery
(CDR) PLL to lock to the reference clock.
0x66 [31:0] RO
pma_rx_is_
lockedtodata
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode.
0x67 [31:0] RO
pma_rx_is_
lockedtoref
When asserted, indicates that the RX CDR PLL is
locked to the reference clock.
Table 4-21: PMA Registers - TX and RX Serial Data Interface
The following PMA registers allow you to customize the TX and RX serial data interface
Address Bit R/W Name Description
0xA8
0 RW
tx_invpolarity
When set to 1, the TX interface inverts the polarity of the
TX data. Inverted TX data is output from the 8B/10B
encoder.
1 RW
rx_invpolarity
When set to 1, the RX channels inverts the polarity of the
received data. Inverted RX data is input to the 8B/10B
decoder.
2 RW
rx_bitreversal_enable
When set to 1, enables bit reversal on the RX interface.
The RX data is input to the word aligner.
3 RW
rx_bytereversal_
enable
When set, enables byte reversal on the RX interface. The
RX data is input to the byte deserializer.
4 RW
force_electrical_idle
When set to 1, forces the TX outputs to electrical idle.
0xA9
0 R
rx_syncstatus
When set to 1, indicates that the word aligner is
synchronized to incoming data.
1 R
rx_patterndetect
When set to 1, indicates the 1G word aligner has detected
a comma.
2 R
rx_rlv
When set to 1, indicates a run length violation.
3 R
rx_rmfifodatainserted
When set to 1, indicates the rate match FIFO inserted
code group.
4 R
rx_rmfifodatadeleted
When set to 1, indicates that rate match FIFO deleted
code group.
5 R
rx_disperr
When set to 1, indicates an RX 8B/10B disparity error.
6 R
rx_errdetect
When set to 1, indicates an RX 8B/10B error detected.
PCS Registers
These registers provide PCS status information.
4-48 PCS Registers
UG-01080
2015.01.19
Altera Corporation Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
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