Altera Transceiver PHY IP Core User Manual
Page 315
Parameter
Range
Description
Enable rx_std_byteorder_ena port
On/Off
Enables the optional
rx_std_byte_order_
ena
control input port. When this signal is
asserted, the byte ordering block initiates a
byte ordering operation if the Byte ordering
control mode is set to manual. Once byte
ordering has occurred, you must deassert and
reassert this signal to perform another byte
ordering operation. This signal is an synchro‐
nous input signal; however, it must be
asserted for at least 1 cycle of
rx_std_clkout
.
Enable rx_std_byteorder_flag port
On/Off
Enables the optional
rx_std_byteorder_
flag
status output port. When asserted,
indicates that the byte ordering block has
performed a byte order operation. This signal
is asserted on the clock cycle in which byte
ordering occurred. This signal is synchronous
to the
rx_std_clkout clock
.
Byte Serializer and Deserializer
The byte serializer and deserializer allow the PCS to operate at twice the data width of the PMA serializer.
This feature allows the PCS to run at a lower frequency and accommodate a wider range of FPGA
interface widths. The following table describes the byte serialization and deserialization options you can
specify.
Table 12-13: Byte Serializer and Deserializer Parameters
Parameter
Range
Description
Enable TX byte serializer
On/Off
When you turn this option On, the PCS
includes a TX byte serializer which allows the
PCS to run at a lower clock frequency to
accommodate a wider range of FPGA
interface widths.
Enable RX byte deserializer
On/Off
When you turn this option On, the PCS
includes an RX byte deserializer and deserial‐
izer which allows the PCS to run at a lower
clock frequency to accommodate a wider
range of FPGA interface widths.
8B/10B
The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. In 8-bit
width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or data
word) with proper disparity. The 8B/10B decoder decodes the data into an 8-bit data and 1-bit control
identifier. The following table describes the 8B/10B encoder and decoder options.
UG-01080
2015.01.19
Standard PCS Parameters for the Native PHY
12-17
Stratix V Transceiver Native PHY IP Core
Altera Corporation