Altera Transceiver PHY IP Core User Manual
Page 347
Name
Direction
Description
tx_parallel_data[
Input
PCS TX parallel data. Used when you enable
either the Standard or 10G datapath. For the
Standard datapath, if you turn on Enable
simplified data interface ,
tx_parallel_
data
includes only the data and control
signals necessary for the current configura‐
tion. Dynamic reconfiguration of the
interface is not supported. For the 10G PCS,
if the parallel data interface is less than 64
bits wide, the low-order bits of tx_parallel_
data are valid. For the 10G PCS operating in
66:40 Basic mode, the 66 bus is formed as
follows: { tx_parallel_data[63:0],tx_10g_
control[0], tx_10g_control[1]}.
For the Standard PCS, refer to Table 12-39:
Signal Definiations for tx_parallel_data with
and with 8B/10B Encoding for bit
definitions. Refer to Table 12-40: Location of
Valid Data Words for tx_parallel_data for
Various FPGA Fabric to PCS Parameteriza‐
tions for various parameterizations.
rx_parallel_data[
Output
PCS RX parallel data. Used when you enable
either the Standard or 10G datapath. For the
Standard datapath, if you turn on Enable
simplified data interface ,
rx_parallel_
data
includes only the data and control
signals necessary for the current configura‐
tion. Dynamic reconfiguration of the
interface is not supported. For the 10G PCS,
if the parallel data interface is less than 64
bits wide, the low-order bits of
rx_
parallel_data
are valid. For the 10G PCS
operating in 66:40 mode, the 66 bus is
formed as follows: { rx_parallel_
data[63:0],rx_10g_control[0], rx_10g_
control[1]}.
For the Standard PCS, refer to Table 12-41:
Signal Definitions for rx_parallel_data with
and without 8B/10B Encoding for bit
definitions. Refer to Table 12-42: Location of
Valid Data Words for rx_parallel_data for
Various FPGA Fabric to PCS Parameteriza‐
tions for various parameterizations.
QPI
UG-01080
2015.01.19
Common Interface Ports for Stratix V Native PHY
12-49
Stratix V Transceiver Native PHY IP Core
Altera Corporation