Altera Transceiver PHY IP Core User Manual
Page 445
Parameter
Range
Description
Enable RX FIFO alignment word deletion
(interlaken)
On/Off
When you turn this option On, all
alignment words (sync words),
including the first sync word, are
removed after frame synchronization is
achieved. If you enable this option, you
must also enable control word deletion.
Enable RX FIFO control word deletion
(interlaken)
On/Off
When you turn this option On , the
rx_
control_del
parameter enables or
disables writing the Interlaken control
word to RX FIFO. When disabled, a
value of 0 for
rx_control_del
writes all
control words to RX FIFO. When
enabled, a value of 1 deletes all control
words and only writes the data to the RX
FIFO.
Enable rx_10g_fifo_data_valid port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_data_valid
signal
which Indicates when
rx_data
is valid.
This option is available when you select
the following parameters:
• 10G PCS protocol mode is Interlaken
• 10G PCS protocol mode is Basic and
RX FIFO mode is phase_comp
• 10G PCS protocol mode is Basic and
RX FIFO mode is register
Enable rx_10g_fifo_full port
On/Off
When you turn this option On, the 10G
PCS includes the active high
rx_10g_
fifo_full
port.
rx_10g_fifo_full
is
synchronous to
rx_clkout
.
Enable rx_10g_fifo_pfull port
On/Off
When you turn this option On, the 10G
PCS includes the active high
rx_10g_
fifo_pfull
port.
rx_10g_fifo_pfull
is synchronous to
rx_clkout
.
Enable rx_10g_fifo_empty port
On/Off
When you turn this option On, the 10G
PCS includes the active high
rx_10g_
fifo_empty
port.
Enable rx_10g_fifo_pempty port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_fifo_pempty
port.
Enable rx_10g_fifo_del port
(10GBASE-R)
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_fifo_del
port. This signal is asserted when a word
is deleted from the RX FIFO. This signal
is only used for the 10GBASE-R
protocol.
14-34
10G PCS Parameters for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation
Arria V GZ Transceiver Native PHY IP Core