Altera Transceiver PHY IP Core - Manual (Page 349)

Name Direction Description
rx_set_locktoref[ -1:0]
Input When asserted, programs the RX CDR to
manual lock to reference mode in which
you control the reset sequence using the
rx_
setlocktoref
and
rx_setlocktodata
.
Refer to Reset Sequence for CDR in Manual
Lock Mode in Transceiver Reset Control in
Stratix V Devices for more information
about manual control of the reset sequence.
pll_locked[
-1:0]
Output When asserted, indicates that the PLL is
locked to the input reference clock.
rx_is_lockedtodata[ -1:0]
Output When asserted, the CDR is locked to the
incoming data.
rx_is_lockedtoref[ -1:0]
Output When asserted, the CDR is locked to the
incoming reference clock.
rx_clkslip[ -1:0]
Input When you turn this option on, the deserial‐
izer performs clock slip operation to acheive
word alignment. The clock slip operation
alternates between skipping 1 serial bit and
pausing the serial clock for 2 cycles to
achieve word alignment. As a result, the
period of the parallel clock could be
extended by 2 unit intervals (UI) during the
clock slip operation. This is an optional
control input signal.
Reconfig Interface Ports
reconfig_to_xcvr [( 70-1):
0]
Input Reconfiguration signals from the
Transceiver Reconfiguration Controller.
grows linearly with the number of
reconfiguration interfaces.
reconfig_from_xcvr [( 46-1)
:0]
Output Reconfiguration signals to the Transceiver
Reconfiguration Controller. grows
linearly with the number of reconfiguration
interfaces.
tx_cal_busy[ -1:0]
Output When asserted, indicates that the initial TX
calibration is in progress. It is also asserted
if reconfiguration controller is reset. It will
not be asserted if you manually re-trigger
the calibration IP. You must hold the
channel in reset until calibration completes.
rx_cal_busy[ -1:0]
Output When asserted, indicates that the initial RX
calibration is in progress. It is also asserted
if reconfiguration controller is reset. It will
not be asserted if you manually re-trigger
the calibration IP.
UG-01080
2015.01.19
Common Interface Ports for Stratix V Native PHY 12-51
Stratix V Transceiver Native PHY IP Core Altera Corporation
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