Xcvr_rx_enable_linear_equalizer_pciemode, Xcvr_rx_sd_enable – Altera Transceiver PHY IP Core User Manual
Page 639
Description
Receiver buffer common-mode voltage.
Note: Contact Altera for using this assignment.
Related Information
XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
Pin Planner and Assignment Editor Name
Receiver Linear Equalizer Control (PCI Express)
Description
If enabled equalizer gain control is driven by the PCS block for PCI Express. If disabled equalizer gain
control is determined by the
XCVR_RX_LINEAR_EQUALIZER_SETTING
Options
TRUE
FALSE
Assign To
Pin - RX serial data
XCVR_RX_SD_ENABLE
Pin Planner and Assignment Editor Name
Receiver Signal Detection Unit Enable/Disable
Description
Enables or disables the receiver signal detection unit. During normal operation
NORMAL_SD_ON=FALSE
,
otherwise
POWER_DOWN_SD=TRUE
.
Used for the PCIe PIPE PHY, SATA and SAS protocols.
Options
FALSE
TRUE
Assign To
Pin - RX serial data
UG-01080
2015.01.19
XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
19-45
Analog Parameters Set Using QSF Assignments
Altera Corporation
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