Altera Transceiver PHY IP Core - Manual (Page 465)

Figure 14-6: Standard PCS Interfaces
Clocks
Word
Aligner
Phase
Compensation
FIFO
Byte
Ordering
Rate
Match FIFO
Polarity
Inversion
PMA
Ports
Standard PCS Interface Ports
rx_std_bitrev_ena[-1:0]
tx_std_bitslipboundarysel[5-1:0]
rx_std_bitslipboundarysel[5< n>-1:0]
rx_std_runlength_err[-1:0]
rx_std_wa_patternalign[-1:0]
rx_std_comdet_ena[-1:0]
rx_std_wa_a1a2size[-1:0]
rx_std_bitslip[-1:0]
tx_std_elecidle[-1:0]
rx_std_signaldetect[-1:0] rx_std_byterev_ena[-1:0]
Byte Serializer &
Deserializer
tx_std_clkout[-1:0]
rx_std_clkout[-1:0]
tx_std_coreclkin[-1:0]
rx_std_coreclkin[-1:0]
rx_std_pcfifo_full[-1:0]
rx_std_pcfifo_empty[-1:0]
tx_std_pcfifo_full[-1:0]
tx_std_pcfifo_empty[-1:0]
rx_std_byteorder_ena[-1:0]
rx_std_byteorder_flag[-1:0]
rx_std_rmfifo_empty[-1:0]
rx_std_rmfifo_full[-1:0]
rx_std_polinv[-1:0]
tx_std_polinv[-1:0]
Table 14-43: Standard PCS Interface Ports
Name Dir Synchro‐
nous to tx_
std_
coreclkin/
rx_std_
coreclkin
Description
Clocks
tx_std_clkout[-1:0] Output — TX Parallel clock output.
rx_std_clkout[-1:0] Output — RX parallel clock output. The CDR
circuitry recovers RX parallel clock from
the RX data stream.
tx_std_coreclkin[-1:0] Input — TX parallel clock input from the FPGA
fabric that drives the write side of the TX
phase compensation FIFO.
rx_std_coreclkin[-1:0] Input — RX parallel clock that drives the read side
of the RX phase compensation FIFO.
Phase Compensation FIFO
rx_std_pcfifo_full[-
1:0]
Output Yes RX phase compensation FIFO full status
flag.
14-54 Standard PCS Interface Ports
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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