Altera Transceiver PHY IP Core - Manual (Page 4)

1G/10GbE Control and Status Interfaces............................................................................................... 5-12
Register Interface Signals..........................................................................................................................5-14
1G/10GbE PHY Register Definitions .....................................................................................................5-15
PMA Registers............................................................................................................................................5-16
PCS Registers..............................................................................................................................................5-17
1G/10 GbE GMII PCS Registers.............................................................................................................. 5-18
PMA Registers............................................................................................................................................5-20
1G/10GbE Dynamic Reconfiguration from 1G to 10GbE...................................................................5-21
1G/10GbE PHY Arbitration Logic Requirements.................................................................................5-22
1G/10GbE PHY State Machine Logic Requirements............................................................................5-23
Editing a 1G/10GbE MIF File ................................................................................................................. 5-23
Creating a 1G/10GbE Design...................................................................................................................5-24
Dynamic Reconfiguration Interface Signals.......................................................................................... 5-25
1G/10 Gbps Ethernet PHY IP Core.........................................................................................................5-27
Design Example..........................................................................................................................................5-29
Simulation Support....................................................................................................................................5-30
TimeQuest Timing Constraints...............................................................................................................5-30
Acronyms....................................................................................................................................................5-30
XAUI PHY IP Core............................................................................................. 6-1
XAUI PHY Release Information............................................................................................................... 6-2
XAUI PHY Device Family Support...........................................................................................................6-2
XAUI PHY Performance and Resource Utilization for Stratix IV Devices.........................................6-3
XAUI PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices............. 6-3
Parameterizing the XAUI PHY..................................................................................................................6-3
XAUI PHY General Parameters................................................................................................................ 6-4
XAUI PHY Analog Parameters..................................................................................................................6-6
XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV
Devices..................................................................................................................................................... 6-6
Advanced Options Parameters.................................................................................................................. 6-8
XAUI PHY Configurations........................................................................................................................ 6-9
XAUI PHY Ports........................................................................................................................................6-10
XAUI PHY Data Interfaces...................................................................................................................... 6-11
SDR XGMII TX Interface............................................................................................................. 6-12
SDR XGMII RX Interface............................................................................................................. 6-13
Transceiver Serial Data Interface.................................................................................................6-13
XAUI PHY Clocks, Reset, and Powerdown Interfaces.........................................................................6-13
XAUI PHY PMA Channel Controller Interface....................................................................................6-15
XAUI PHY Optional PMA Control and Status Interface.................................................................... 6-16
XAUI PHY Register Interface and Register Descriptions....................................................................6-18
XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and
Stratix IV GX.........................................................................................................................................6-25
XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V
Devices...................................................................................................................................................6-25
Logical Lane Assignment Restriction..........................................................................................6-26
XAUI PHY Dynamic Reconfiguration Interface Signals......................................................... 6-26
SDC Timing Constraints.......................................................................................................................... 6-27
Simulation Files and Example Testbench...............................................................................................6-27
TOC-4 Altera Transceiver PHY IP Core User Guide
Altera Corporation