Altera Transceiver PHY IP Core - Manual (Page 48)

Table 3-15: Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk
Input The clock signal that controls the Avalon-MM
PHY management, interface. For Stratix IV
devices, the frequency range is 37.5-50 MHz.
There is no frequency restriction for Stratix V
devices; however, if you plan to use the same clock
for the PHY management interface and
transceiver reconfiguration, you must restrict the
frequency range of
phy_mgmt_clk
to 100-150
MHz to meet the specification for the transceiver
reconfiguration clock.
phy_mgmt_clk_reset
Input Global reset signal that resets the entire 10GBASE-
R PHY. This signal is active high and level
sensitive. This signal is not synchronized
internally.
phy_mgmt_addr[8:0]
Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input Input data.
phy_mgmt_readdata[31:0]
Output Output data.
phy_mgmt_write
Input Write signal. Asserted high.
phy_mgmt_read
Input Read signal. Asserted high.
phy_mgmt_waitrequest
Output When asserted, indicates that the Avalon-MM
slave interface is unable to respond to a read or
write request. When asserted, control signals to
the Avalon-MM slave interface must remain
constant.
Refer to the “Typical Slave Read and Write Transfers” and “Master Transfers” sections in the “Avalon
Memory-Mapped Interfaces” chapter of the Avalon Interface Specifications for timing diagrams.
The following table specifies the registers that you can access over the Avalon-MM PHY management
interface using word addresses and a 32-bit embedded processor. A single address space provides access
to all registers.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 3-16: 10GBASE-R Register Descriptions
Word Addr Bit R/W Name Description
PMA Common Control and Status
3-24 10GBASE-R PHY Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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