Altera Transceiver PHY IP Core - Manual (Page 234)

Table 9-13: Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCS
Parameterizations
The following table shows the valid 11-bit data words with and without the byte deserializer for single- and
double-word FPGA fabric to PCS interface widths. The byte serializer allows the PCS to operate at twice the data
width of the PMA . This feature allows the PCS to run at a lower frequency and accommodates a wider range of
FPGA interface widths.
Configuration Bus Used Bits
Single word data bus, byte deserializer disabled [10:0] (word 0)
Single word data bus, byte serializer enabled [32:22], [10:0] (words 0 and 2)
Double word data bus, byte serializer disabled [21:0] (words 0 and 1)
Double word data bus, byte serializer enabled [43:0] (words 0-3)
UG-01080
2015.01.19
Data Interfaces 9-21
Custom PHY IP Core Altera Corporation
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