Altera Transceiver PHY IP Core User Manual
Page 226
Name
Value
Description
Enable byte ordering block
manual control
On/Off
Turn this option on to choose manual control
of byte ordering. This option creates the
rx_
enabyteord
signal. A byte ordering operation
occurs whenever
rx_enabyteord
is asserted.
To perform multiple byte ordering
operations, deassert and reassert
rx_
enabyteord
.
Byte ordering pattern
Depends on
configuration
Specifies the pattern that identifies the SOP.
For 16-bit byte ordering pattern you must
include a 2-bit pad so that the pattern entered
is in the following format: 00
pattern is 10111100, enter the following
pattern: 00101111000010111100
Enter the byte ordering pattern as follows
based on the 5 configurations that support
byte ordering as described in the Enable byte
ordering block:
• Configuration 1: 8-bits
• Configuration 2: 10-bits
For example: If you select a /Kx.y/ control
code group as the byte ordering pattern,
the most significant 2 bits of the 10-bit
byte ordering pattern must be 2'b01. If you
select a /Dx.y/ data code group as the byte
ordering pattern, the most significant 2-
bits of the 10-bit byte ordering pattern
must be 2'b00. The least significant 8-bits
must be the 8B/10B decoded version of the
code group used for byte ordering.
• Configuration 3:16-bits, 8-bits
• Configuration 4: 18-bits
• Configuration 5: 20-bits, 10-bits
For example: If you select a /Kx.y/Dx.y/
code group as the byte ordering pattern,
the most significant 2-bits of the 20-bit
byte ordering pattern must be 2'b01.
Similarly bit[9:0] must be 2'b00. Bit[18:10]
must be the 8B/10B decoded version of /
Kx.y/. Bit[7:0] must be 8B/10B decoded
version of /Dx.y/.
UG-01080
2015.01.19
Byte Order Parameters
9-13
Custom PHY IP Core
Altera Corporation