Altera Transceiver PHY IP Core - Manual (Page 145)

Name Value Description
XAUI interface type
Hard XAUI
Soft XAUI
DDR XAUII The following 3 interface types are available:
• Hard XAUI–Implements the PCS and
PMA in hard logic. Available for Arria II,
Cyclone IV, HardCopy IV, and Stratix IV
devices.
• Soft XAUI–Implements the PCS in soft
logic and the PMA in hard logic. Available
for HardCopy IV, Stratix IV, Arria V,
Cyclone V, and Stratix V devices.
• DDR XAUI–Implements the PCS in soft
logic and the PMA in hard logic. Both the
application and serial interfaces run at twice
the frequency of the Soft XAUI options.
Available for HardCopy IV Stratix IV
devices.
All interface types include 4 channels.
Data rate Device Dependent Specifies the data rate.
PLL type
CMU
ATX You can select either the CMU or ATX PLL.
The CMU PLL has a larger frequency range
than the ATX PLL. The ATX PLL is designed
to improve jitter performance and achieves
lower channel-to-channel skew; however, it
supports a narrower range of data rates and
reference clock frequencies. Another advantage
of the ATX PLL is that it does not use a
transceiver channel, while the CMU PLL does.
This parameter is available for the soft PCS and
DDR XAUI.
The ATX PLL is not available for all devices.
Base data rate
1 × Lane rate
2 × Lane rate
4 × Lane rate
The base data rate is the frequency of the clock
input to the PLL. Select a base data rate that
minimizes the number of PLLs required to
generate all the clock s required for data
transmission. By selecting an appropriate base
data rate, you can change data rates by
changing the divider used by the clock
generation block. This parameter is available
for Stratix V devices.
Number of XAUI
interfaces
1 Specifies the number of XAUI interfaces. Only
1 is available in the current release.
UG-01080
2015.01.19
XAUI PHY General Parameters 6-5
XAUI PHY IP Core Altera Corporation
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