Altera Transceiver PHY IP Core - Manual (Page 499)

Note: If you have the auto-negotiation state machine in your transceiver design, please note that the rate
match FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets
during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered
sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base
Support Solution .
Table 15-13: Status Flag Mappings for Simplified Native PHY Interface
Status Condition Protocol Mapping of Status Flags to RX Data Value
Full
PHY IP Core for PCI
Express (PIPE)
Basic double width
RXD[62:62] = rx_
rmfifostatus[1:0]
, or
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[30:29] = rx_
rmfifostatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b11 = full
XAUI, GigE, Serial RapidIO
double width
rx_std_rm_fifo_full 1'b1 = full
All other protocols Depending on the FPGA fabric to
PCS interface width either:
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b11 = full
15-16 Rate Match FIFO
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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