Xaui phy configurations, Xaui phy configurations -9 – Altera Transceiver PHY IP Core User Manual
Page 149
XAUI PHY Configurations
This section describes configurations of the IP core.
The following figure illustrates one configuration of the XAUI IP Core. As this figure illustrates, if your
variant includes a single instantiation of the XAUI IP Core, the transceiver reconfiguration control logic is
included in the XAUI PHY IP Core. For Arria V, Cyclone V, and Stratix V devices the Transceiver
Reconfiguration Controller must always be external. Refer to Chapter 16, Transceiver Reconfiguration
Controller IP Core for more information about this IP core. The Transceiver Reconfiguration Controller
is always separately instantiated in Stratix V and Arria V GZ devices.
Figure 6-2: XAUI PHY with Internal Transceiver Reconfiguration Control
System
Interconnect
Fabric
Inter-
leave
PCS
S
Alt_PMA
S
S
Low Latency
Controller
S
Transceiver
Reconfiguration
Controller
Transceiver Channel
Hard XAUI PHY
4 x 3.125 Gbps serial
to Embedded
Controller
4
4
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
M
Avalon-MM
PHY
Mgmt
S
PMA Channel
Controller
Related Information
Transceiver Reconfiguration Controller IP Core Overview
UG-01080
2015.01.19
XAUI PHY Configurations
6-9
XAUI PHY IP Core
Altera Corporation